NXP i.MX RT1170
The NXP i.MXRT1170 devices are dual core MCUs with an ARM Cortex-M7 and Cortex-M4 core.
QSPI support
The RT117x does not come with internal flash but with external flash connected to the FlexSPI bus, only. The external FlexSPI controller allows to connect several different flash types like QSPI, HyperFlash and Octaflash. Furthermore, the external flash can be connected to different pin / ports of the FlexSPI controller which makes a auto-detection very difficult thus an out-of-the-box solution which works for all setups is kind of impossible. For that reason, the J-Link software supports the evaluation board setup, only. Other setups may work but without any warranty or guarantee from SEGGER. If you are working with a different setup and looking for support for this setup, please get in touch with SEGGER.
Supported FlexSPI1 pin configurations
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for FlexSPI1. For details on how to select a specific flash loader, please see here.
| Signal = Pin | Loader name | Supported since software version |
|---|---|---|
| FLEXSPI_SS0 = GPIO_SD_B2_06 FLEXSPI_SCLK = GPIO_SD_B2_07 FLEXSPI_DATA0 = GPIO_SD_B2_08 FLEXSPI_DATA1 = GPIO_SD_B2_09 FLEXSPI_DATA2 = GPIO_SD_B2_10 FLEXSPI_DATA3 = GPIO_SD_B2_11 |
nCS@SDB206_CLK@SDB207_D0@SDB208_D1@SDB209_D2@SDB210_D3@SDB211 | V6.64 |
| FLEXSPI_SS0 = GPIO_AD_18 FLEXSPI_SCLK = GPIO_AD_19 FLEXSPI_DATA0 = GPIO_AD_20 FLEXSPI_DATA1 = GPIO_AD_21 FLEXSPI_DATA2 = GPIO_AD_22 FLEXSPI_DATA3 = GPIO_AD_23 |
nCS@AD18_CLK@AD19_D0@AD20_D1@AD21_D2@AD22_D3@AD23 | V7.88l |
Supported FlexSPI2 pin configurations
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports one pin configuration for FlexSPI2.
| Signal = Pin | Loader name | Supported since software version |
|---|---|---|
| FLEXSPI_SS0 = GPIO_SD_B1_00 FLEXSPI_SCLK = GPIO_SD_B1_01 FLEXSPI_DATA0 = GPIO_SD_B1_02 FLEXSPI_DATA1 = GPIO_SD_B1_03 FLEXSPI_DATA2 = GPIO_SD_B1_04 FLEXSPI_DATA3 = GPIO_SD_B1_05 |
nCS@SDB100_CLK@SDB101_D0@SDB102_D1@SDB103_D2@SDB104_D3@SDB105 | V7.82d |
| FLEXSPI_SS0 = GPIO_EMC_B2_11 FLEXSPI_SCLK = GPIO_EMC_B2_10 FLEXSPI_DATA0 = GPIO_EMC_B2_13 FLEXSPI_DATA1 = GPIO_EMC_B2_14 FLEXSPI_DATA2 = GPIO_EMC_B2_15 FLEXSPI_DATA3 = GPIO_EMC_B2_16 |
nCS@EMCB211_CLK@EMCB210_D0@EMCB213_D1@EMCB214_D2@EMCB215_D3@EMCB216 | V8.12a |
Reset
Rev A0 or later silicon:
When the RT1170 rev A is reset via debugger (SYSRESET_REQ), the boot ROM will not jump to the flash application although it is valid but enter a debug loop at a fixed PC address (0x00223104 for Rev A0, 0x002231FC for Rev B0). The debugger then needs to initialize PC and SP manually in order to jump to the user application. After reset J-Link checks the silicon revision and PC and if these match the expected values, J-Link determines the boot configuration by reading SRC_SBMR1 register. If booting from FlexSPI1,
J-Link reads initial SP/PC from 0x30002000/0x30002004 (0x60002000/0x60002004 for FlexSPI2) and sets SP/PC to the values read from flash.