NXP i.MX 7D

The NXP i.MX 7S (Solo) and 7D (Dual) are multi-core MCUs composed of an ARM Cortex-M4 and one or two Cortex-A7 cores.

Flash Banks

Flash Bank	Base address	Size	J-Link Support
QSPI flash	0x60000000	Up to 128 MB

QSPI flash programming support

QSPI flash programming support is included since software version V6.32. It allows to program any common SPI flash connected to the QSPI controller. Programming is supported out-of-the-box thus no additional scripts are required. A detailed list of all supported SPI flashes can be found here: https://www.segger.com/products/debug-probes/j-link/technology/cpus-and-devices/supported-spi-flashes/

Multi-core support for i.MX 7D

J-Link script files are necessary to connect to both A7 cores and the M4 core of the iMX7D MCU.

• A7 core0: File:NXP iMX7D Connect CortexA7 0.JLinkScript
• A7 core1: File:NXP iMX7D Connect CortexA7 1.JLinkScript
• M4 core: File:NXP iMX7D Connect CortexM4.JLinkScript

Example package for J-Link Commander:

• File:NXP iMX7D JLinkCommander ExamplePackage.zip

How to use script files: Please refer to J-Link User Guide (UM08001), chapter 5.11 "J-Link script files"

Startup procedure is:

1)     Start debug session that connects to A7_0
2)     Start debug session that connects to A7_1
3)     Start debug session that connects to M4
[...]
x)     Close debug session that connects to M4
x + 1) Close debug session that connects to A7_1
x + 2) Close debug session that connects to A7_0

Important!

On the iMX7D the A7_1 core cannot be independently debugged without enabling the core by either having something running on the A7_0 or M4 that enables the A7_1 or as part of the A7_0 J-Link script file. In the example script file above, we chose the later case to enable the A7_1 core from within the A7_0 J-Link script file.

Cortex-M4 core

M4 Debug Application (Example)

In order to debug an application running on the M4, the application needs to be loaded on the Cortex-M4 using the Cortex-A7. This can be done either by the application running on the A7 core or by loading the code manually (e.g. using J-Link Commander). A step-by-step instruction with detailed information is provided by NXP in the Application Note AN5317 (https://www.nxp.com/docs/en/application-note/AN5317.pdf). A short step-by-step instruction which shows how to reload & debug the code on the M4 using J-Link Commander is given below. The used application is part of the FreeRTOS example, available for download on the NXP webpage. The example has been created to run on the MCIMX7SABRE evaluation board (red LED D10 blinks): File:blinking imx demo gpt.zip. The example assumes that a UART connection to the debug UART of the M4 is open.

1. Prepare the debug UART
   1. Supply power to the MCIMX7SABRE evaluation board
   2. Connect the DEBUG UART via USB to the PC
   3. Connect to the M4 debug UART using a terminal application (e.g. HTerm; COMxxx; Baud: 115200; Data: 8; Stop: 1; Parity: None)
2. Download the application to the M4 through the A7
   1. Start J-Link Commander and connect to the A7 main core by selecting "MCIMX7D7_A7_0" as target device
   2. Halt the CPU using the h command in J-Link Commander
   3. Issue a software reset of the M4 (w4 0x3039000C 0xAC)
   4. Load the M4 application code to the TCM_L memory space (loadfile blinking_imx_demo_gpt.bin,0x007F8000)
   5. Set PC and SP according to the build M4 application (In this example: w4 0x00180000 0x20008000 and w4 0x00180004 0x1FFFACFD
   6. Perform a software reset of the M4 core in order to start the application (w4 0x3039000C 0xAA)
3. If the application has been started successfully, the red LED (D10) starts blinking
   1. Start J-Link Commander and connect to the M4 core using the iMX7D_Connect_CortexM4.JLinkScript J-Link script file
   2. Issue a halt request using the h command in J-Link Commander --> LED stops blinking
   3. Let the application run again using the go command in J-Link Commander --> LED starts blinking again

Debugging in OCRAM

The i.MX7 series devices incorporate a device-specific cache unit that is controlled via the LMEM peripheral/module. In order to allow settings software breakpoints when debugging in RAM, the LMEM module should be disabled. When debugging in OCRAM on the M4 core, the LMEM module needs to be disabled to set any breakpoint. This is needed because the OCRAM is above addr. 0x1FFFFFFF which is the max. address for which HW breakpoints can be used on the M4. This means, for OCRAM debugging, always software breakpoints would be used on the M4 and this requires LMEM to be disabled.

Note: This might be handled automatically by a future J-Link software version but there are no immediate plans yet.

Tracing on NXP iMX7D7

This section describes how to get started with trace on the NXP iMX7D7 MCUs. This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001).

Note:

Some of the examples are shipped with a compiled .JLinkScriptfile (extension .pex), should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.

To create your own .JLinkScriptfile you can use the following guide as reference: How_to_configure_JLinkScript_files_to_enable_tracing

Minimum requirements

In order to use trace on the NXP iMX7D7 MCU devices, the following minimum requirements have to be met:

• J-Link software version V7.98h or later
• Ozone V3.36 or later (if streaming trace and / or the sample project from below shall be used)
• J-Trace PRO for Cortex-M HW version V3.0 or later for streaming trace
• J-Link Plus V12 or later for TMC/ETB trace

To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V8.16. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.

Cortex-A7 0

The project below has been tested with the minimum requirements mentioned above and a MCIMX7SABRE.

• Example project: NXP_IMX7D7_A7_0_TraceBuffer.zip

Trace buffer (TMC/ETB)

Open the *_TraceBuffer.jdebug project contained in the example project in Ozone.

Cortex-A7 1

The project below has been tested with the minimum requirements mentioned above and a MCIMX7SABRE.

• Example project: NXP_IMX7D7_A7_1_TraceBuffer.zip

Trace buffer (TMC/ETB)

Open the *_TraceBuffer.jdebug project contained in the example project in Ozone.

Tested Hardware

MCIMX7SABRE

Specifics/Limitations

The iMX7D series supports pin tracing by chip design. Since the evaluation board does not route these pins to a trace connector, we could not evaluate this and have thus not prepared an example. If you are interested in pin tracing this device, please refer our guide How_to_configure_JLinkScript_files_to_enable_tracing.