NXP i.MX 6SX
(Redirected from i.MX6SoloX)
Jump to navigation
Jump to search
The NXP i.MX 6SX (SoloX) are multi-core MCUs composed of a Cortex-M4 and Cortex-A9 core.
Flash Banks
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| QSPI flash | 0x70000000 | Up to 256 MB | 
|
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports the following pin configurations for iMX6SoloX:
| Alternate function | Port / Pin |
|---|---|
| QSPI2A_SS0_B | IOMUXC_SW_MUX_CTL_PAD_NAND_ALE |
| QSPI2A_DATA2 | IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B |
| QSPI2A_DATA3 | IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B |
| QSPI2A_SCLK | IOMUXC_SW_MUX_CTL_PAD_NAND_CLE |
| QSPI2A_DATA1 | IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B |
| QSPI2A_DATA0 | IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B |
Watchdog Handling
The device has a watchdog timer WDOG that is not handled and must be disabled during flash programming.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The iMX6SoloX family feature a Cortex-A9 and Cortex-M4 core.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cortex-A9
Init/Setup
- Enables debugging
Reset
- No Reset is performed.
Secondary core(s)
Init/Setup
- Enables debugging
Reset
- No reset is performed.