Microchip PolarFire SOC
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The Microchip PolarFire family are RISC-V(RV64) based microcontrollers.
Flash Banks
| Flash Bank | Base address | J-Link Support | Loader | |
|---|---|---|---|---|
| Name | Size | |||
| External Flash | 0xXXXX_XXXX | 
|
- | - |
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The [DeviceFamily]family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.
Some of the are available with enabled lockstep mode, only.
| Core | J-Link Support |
|---|---|
| E51 | 
|
| 4 x U54 |
|
In below, the debug related multi-core behavior of the J-Link is described for each core:
E51 core
Reset
- RISC-V generic reset is performed.
Attach
- Attach is supported.
U54 core(s)
Reset
No reset is performed.
Attach
- Attach is supported.
Device Specific Handling
Connect
Reset
- The device uses normal RISC-V reset, no special handling necessary, like described here.