NXP LPC54xx
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The NXP LPC54 are Cortex-M4 based microcontrollers.
Flash Banks
| Flash Bank | Base address | J-Link Support | Loader | |
|---|---|---|---|---|
| Name | Size | |||
| External QSPI [1] | [Address] | 
|
Default | Up to 128 MB |
- ↑
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for this Device. The default loader is marked in bold. For details on how to select a specific flash loader, please see here.
SRAM
For power saving reasons, the SRAM is devided in sections (SRAM0 - SRAM3), which can be clocked and powered separately. By default (after reset), only SRAM0 is clocked and powered. Clocks and power of the separate SRAM sections can be controlled via the AHB Clock Control register 0 and the Power Configuration register 0.
RTT
As not all RAM is available by default, only the default SRAM section (SRAM0) is searched for the RTT Control Block. However, the other RAM sections can be added as search ranges by the user via the methods explained in the RTT article > Troubleshooting section.
Device Specific Handling
Connect
- The device uses normal Cortex-M connect sequence.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
Limitations
- For an application to boot from QSPI flash, the image in QSPI flash requires a valid checksum.