ST SR5E1

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The ST Stellar E SR5E1 are dual core Cortex-M7 MCUs with Cortex-M0 HSM.

Supported devices

Refer to the supported device list for a full list of all supported SR5E1 family devices, their corresponding names and connection diagrams.


Target interfaces

Interface J-Link support Flasher support
JTAG YES.png YES.png
SWD YES.png YES.png

Flash Banks

Flash bank Base address J-Link support Flasher support Loader
Name Bank size
Code flash 1 0x08000000 YES.png YES.png [default] 960 KB
Code flash 2 0x080F0000 YES.png YES.png [default] 960 KB
Data flash 0x08F00000 YES.png YES.png [default] 64 KB
HSM code flash 0x18000000 YES.png YES.png [default] 160 KB
HSM data flash 0x18F00000 YES.png YES.png [default] 32 KB
UTEST (OTP) [1] 0x1FF80000 YES.png YES.png [default] 16 KB
  1. These area is not erasable and some ranges are reserved and not readable.
Note:
Flasher standalone mode is not supported yet.
  • Flash programming is available on main core only.

ECC RAM

  • 32 KB ECC RAM at 0x24000000 is initialized on connect.

Watchdog Handling

  • The device has two watchdogs WWDG1 & WWDG2.
  • If the watchdogs are enabled, they are fed during flash programming.

Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The SR5E1 family comes with an optional second core.
By default the second core is in lockstep and has to be released by a DCF.

Core J-Link Support
Cortex-M7 Core 1 YES.png
Cortex-M7 Core 2 YES.png
Cortex-M0 HSM NO.png

In below, the debug related multi-core behavior of the J-Link is described for each core:

Main core

Init/Setup

  • Initializes the ECC RAM, see ECC RAM
  • Enables debugging

Attach

  • Attach is supported if WorkRAM init is skipped.

Secondary core, if available

Init/Setup

  • If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
  • If the secondary core is not enabled yet, it will be enabled / release from reset

Reset

No reset is performed, the core is halted.

  • A generic reset of this core is currently not supported by J-Link. This means that a core reset is not performed when issued by a debugger (e.g. SEGGER Ozone).
    If a reset of this core is required, this needs to be implemented via a customized ResetTarget() J-Link script file function.
    If you are interested in a customized ResetTarget() implemented by SEGGER, please get in touch with us directly: https://www.segger.com/support/technical-support/.

Attach

  • Attach is supported / desired.

HSM core

  • NOT supported.

Device Specific Handling

Reset

  • The device uses normal Cortex-M reset, no special handling necessary, like described here.

Limitations

Security

The Device has multiple security features and a HSM based on a Cortex-M0 core.

Debug Authentication

Authentication via JTAG password is supported by J-Link and will be executed on connect if necessary.
A destructive reset will reset the password and authentication has to be done again.
The JTAG password becomes active when lifecycle, passwords and lock bit [DBL] are set correctly.
Please refer to the security reference manual.

Specifying the JTAG password using J-Link Command String

This is the recommended method as the specified JTAG password will be used for the whole session. This way, the key may not specified multiple times (e.g. if a reset is performed).
The J-Link Command String SetCPUConnectIDCode <Key> needs to be passed to the J-Link DLL before establishing the target connection(see example below).

Example JTAG password:

  • JTAGPassword0: 0x01234567
  • JTAGPassword1: 0x89ABCDEF
  • JTAGPassword2: 0x00224466
  • JTAGPassword3: 0x88AABBCC
  • JTAGPassword4: 0x11335577
  • JTAGPassword5: 0x99DDEEFF
  • JTAGPassword6: 0xA0B1A3B3
  • JTAGPassword7: 0x4D5E6E7D
 exec SetCPUConnectIDCODE 67452301EFCDAB8966442200CCBBAA8877553311FFEEDD99B3A3B1A07D6E5E4D

Specifying the authentication code using the ID Code dialog

This feature will be available soon.

Specifying the JTAG password via J-Link script file

The JTAG password can be specified via J-Link script file as follows:

  JLINK_ExecCommand("SetCPUConnectIDCODE = 67452301EFCDAB8966442200CCBBAA8877553311FFEEDD99B3A3B1A07D6E5E4D");

Because the SR5E1 device already uses InitTarget() and ConfigTargetSettings(), this can only be done via a modified ConfigTargetSettings() function.
Please get in touch with the SEGGER support about the ConfigTargetSettings() for the SR5E1.

Evaluation Boards

Example Application