ST SR5E1
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The ST Stellar E SR5E1 are dual core Cortex-M7 MCUs.
Flash Banks
Internal Flash
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| Code flash 1 | 0x08000000 |  |
|
[default] | 960 KB |
| Code flash 2 | 0x080F0000 | |
|
[default] | 960 KB |
| Data flash | 0x08F00000 | |
|
[default] | 64 KB |
| HSM code flash | 0x18000000 | |
|
[default] | 160 KB |
| HSM data flash | 0x18F00000 | |
|
[default] | 32 KB |
| UTEST (OTP) [1] | 0x1FF80000 | |
|
[default] | 16 KB |
- ↑ These area is not erasable and some ranges are reserved and not readable.
ECC RAM
- 32 KB ECC RAM at 0x24000000 is initialized on connect.
Watchdog Handling
- The device has two watchdogs WWDG1 & WWDG2.
- If the watchdogs are enabled, they are fed during flash programming.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The SR5E1 family comes with an optional second core.
By default the second core is in lockstep and has to be released by a DCF.
| Core | J-Link Support |
|---|---|
| Cortex-M7 Core 1 |
|
| Cortex-M7 Core 2 |
|
In below, the debug related multi-core behavior of the J-Link is described for each core:
Main core
Init/Setup
- Initializes the ECC RAM, see ECC RAM
- Enables debugging
Attach
- Attach is supported if WorkRAM init is skipped.
Secondary core, if available
Init/Setup
- If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
- If the secondary core is not enabled yet, it will be enabled / release from reset
Reset
No reset is performed, the core is halted.
- A generic reset of this core is currently not supported by J-Link. This means that a core reset is not performed when issued by a debugger (e.g. SEGGER Ozone).
If a reset of this core is required, this needs to be implemented via a customized ResetTarget() J-Link script file function.
If you are interested in a customized ResetTarget() implemented by SEGGER, please get in touch with us directly: https://www.segger.com/support/technical-support/.
Attach
- Attach is supported / desired.
Device Specific Handling
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
Limitations
Security
- Device has a HSM based on a Cortex-M0 core.