CVA CHIP CVM014x
The CVA CHIP CVM014x are Cortex-M4 based MCUs which are supported by the J-Link software beginning from V7.92g.
Supported devices
Refer to the supported device list for a full list of all supported CVM014x family devices, their corresponding names and connection diagrams.
Flash banks
Internal flash
CVM0142
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| PFLASH | 0x00000000 |  |
|
Default | 256 KB |
| DFLASH | 0x10010000 | |
|
Default | 64 KB |
CVM0144
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| PFLASH | 0x00000000 | |
|
Default | 512 KB |
| DFLASH | 0x10010000 | |
|
Default | 64 KB |
CVM0146
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| PFLASH | 0x00000000 | |
|
Default | 1024 KB |
| DFLASH | 0x10000000 | |
|
Default | 128 KB |
Info region flash
All devices
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| Info region 0 [1] | 0x00200000 | |
|
Default | 2 KB |
| Info region 1 [2] | 0x00200800 | |
|
Default | 2 KB |
| Info region 2 [1] | 0x00201000 | |
|
Default | 1 KB |
All integrated flashes have ECC which is why reading erased flash areas is to avoid.
For more information refer to the ECC article.
Watchdog handling
- The device has a watchdog WDOG.
- The watchdog is fed during flash programming.
Internal SRAM
Since CVM014x devices have SRAM with ECC, the J-Link software will initialize 0x6400 bytes of SRAM at address 0x20000000 on connect.
For more information refer to the ECC article.
MCU Security
Info Region
The CVM014x series devices provide three Info Regions which allow some "permanent" configuration as well as readout protection for the device. Such Info Regions are not accessible via the AXBS bus, therefore pseudo-addresses are assigned for access via flashloader. Each Info Region consists of multiple configuration fields. After a reset, the values within these fields will be written into the corresponding registers. All complementary bytes are automatically set when writing the Info Region.
In case the device reports a secure state (FTFC_FSTAT[SECURE] != 0x2), the J-Link software will popup a request for an unlock via mass-erase on connect. A mass erase will set the device in an unlocked state.
A mass erase will enable the protection of all flash areas (FTFC_PFPRONT0 = 0xFFFFFFFF, FTFC_PFRONT1 = 0xFFFFFFFFFF, FTFC_DFPRONT = 0x0000FFFF, FTFC_EFPRONT = 0x000100FF).
How to program the Info Region
The J-Link software support native programming of the Info Region. InfoRegion 0 — Contains security configuration fields. Can only be erased by a mass erase operation. Must be programmed with caution, as certain settings can permanently disable access to memory and the debug subsystem. InfoRegion 1 — A one-time programmable, user-defined area. Cannot be erased. InfoRegion 2 — Contains EEPROM configuration fields and a user-defined area. Can only be erased by a mass erase operation.
Security settings and mass erase operations are managed through the Device Provisioner utility: CVA CHIP CVM014x Security
The Info Region will also be protected after a mass erase (FTFC_EFPRONT[SECPROT] = 1). Therefore, unprotecting the Info Region will only succeed when the device has not been power-cycled after a mass erase.
Reset
CVM014x devices have an integrated bootloader which executes before target program execution. While bootloader execution, PFlash can not be accessed from 0x0 - 0xFFF. A special reset strategy is implemented to handle this.
In case there is no target application in program flash, the core will halt in the hardfault state.
Evaluation Boards
- CVA CHIP CVM0146-EVB evaluation board: https://kb.segger.com/CVA_CHIP_CVM0146-EVB