Allegro MicroSystems A892x

The Allegro MicroSystems A892x series are 32-bit microcontrollers based on the Arm® Cortex®-M4 processor.

Flash Banks

A89201KEVSR-A / -E

Flash Bank	Base address	J-Link Support	Loader
			Name	Size
Internal Flash	0x08000000		Default	248 KB

A89201KEVSR-B / -C / -D / -F

Flash Bank	Base address	J-Link Support	Loader
			Name	Size
Internal Flash	0x08000000		Default	128 KB

A89211GEVSR

Flash Bank	Base address	J-Link Support	Loader
			Name	Size
Internal Flash	0x08000000		Default	252 KB

A89211GEVSR-A

Flash Bank	Base address	J-Link Support	Loader
			Name	Size
Internal Flash	0x08000000		Default	128 KB

A89212GEVSR

Flash Bank	Base address	J-Link Support	Loader
			Name	Size
Internal Flash	0x08000000		Default	252 KB

A89212GEVSR-A

Flash Bank	Base address	J-Link Support	Loader
			Name	Size
Internal Flash	0x08000000		Default	128 KB

A89224KEVSR-A / -E

Flash Bank	Base address	J-Link Support	Loader
			Name	Size
Internal Flash	0x08000000		Default	248 KB

A89224KEVSR-B / -F / -H

Flash Bank	Base address	J-Link Support	Loader
			Name	Size
Internal Flash	0x08000000		Default	128 KB

Watchdog Handling

• The device has a watchdog (WDT).
• The watchdog is fed during flash programming if active.

Device Specific Handling

Reset

• The device uses normal Cortex-M reset, no special handling necessary, like described here.

SWD interface

This device's SWD interface is disabled by default. To enable it the TEST pin (also mapped to SWDIO pin) has to be pulled high to VD33 before the MCU is fully powered on (VDD is stable). This can be achieved by using either of the following methods:

Allegro debug daughter board

This board (provided by Allegro) handles the SWD enable sequence automatically when correctly set up. Jumper / switch settings for Allegro SoC EVM Debug Rev1:

Jumper / Switch	Setting
S1	Off - Off
J1	1-2
J2	1-2
J3	1-2

Apart from the jumper / switch setting and connecting the debug daughter board no further special handling is required.

Powered by J-Link directly

When the chip is powered by the J-Link directly (and only then) a special connect code will be executed where the SWD interface will be enabled automatically. In this case the following Pin Setup is required:

J-Link Pin	Allegro chip Pin	Allegro A89201EV EVM Rev2 board
VTref	VD33	X10-3
GND	GND	X10-2
Supply	VD50	X10-1
SWDIO	TEST	X10-4
SWCLK	GPIO_0	X10-5

Note:
When using J-Flash the setting 'Target power supply' (VCC5V) has to be enabled (Options => Project settings => Production) before connecting.

Note:
To avoid hardware damage do not power the chip via VBB at the same time when using this setup (powered by J-Link directly).

Normal power supply without the Allegro debug daughter board

If a pullup resistor (1kΩ) is connected between J-Link's SWDIO (TEST) and VTref (VD33) pins the Allegro daughter board can be omitted and the chip normally powered via VBB.
The SWD interface will be enabled on device power-up, as SWDIO (TEST) is pulled high to VD33.

In this case the following Pin Setup is required:

J-Link Pin	Allegro chip Pin	Allegro A89201EV EVM Rev2 board
VTref	VD33	X10-3
GND	GND	X10-2
SWDIO	TEST	X10-4
SWCLK	GPIO_0	X10-5

Evaluation Boards

• Allegro A89201EV

Example Application

• Allegro A89201EV